An initially designed product, comprising an analog block (i.e. for example a block essentially processing analog signals) and a digital block (i.e. for example a block essentially processing digital signals), may undergo structural and/or functional evolutions resulting in versions in which the size of the digital block has increased. In general, the initial version of the product, possessing an initial footprint, would have been produced in a native technology, for example a 120 nanometer CMOS technology, and the analog part and the digital part of the integrated circuit would be produced within the same substrate, generally with a seal ring, in practice of rectangular shape, surrounding the digital block and the analog block.
It is then particularly advantageous for the final version of the product to be technologically produced, that is to say the version in which the enlarged digital block projects beyond the seal ring, in such a way that at the end the footprint of the product on the substrate is the same, that is to say the modified analog and digital blocks still remain within the seal ring.
When the native technology possesses a shrunken version and the enlargement of the digital block in the final version of the product is not too great compared with the size of the digital block in the initial version of the product, it is then possible to use the shrunken technological version of the native technology to produce the integrated circuit so as in the end to reduce its footprint on the silicon. To give an example, the shrunken version of 120 nanometer CMOS technology is a 110 nanometer CMOS technology.
One approach includes enlarging the size of the analog block so as to apply a homogeneous homothetic reduction towards the shrunken technological version on the entire integrated circuit.
According to this method, the enlargement of the analog block is performed at the design stage of this block so as to obtain, at the design stage, a single digital file (file GDSII for example) representative of both the analog block and the digital block. Furthermore, it is from this single file that mask files are conventionally prepared.
However, such a method has drawbacks. More precisely, before enlargement, the geometric structures of the various elements coincide with the design gate used for the design. However, after enlargement, this coincidence is destroyed. Therefore, a rounding is automatically applied on all the critical geometries so as again to make them coincide with the gate pitch, which may in fine lead to problems. This situation is all the more critical the more advanced the technology, i.e. the finer the etching corresponding to the gate length of the transistors.
Moreover, the design rule checks or DRCs become increasingly difficult to manage and the optical proximity corrections or OPCS run the risk of no longer being controlled (erratic fragmentation).